This core is an universal input / output / bidirectional
controller, width of the outputs are sizeable. The following
modes of operation are available within the GERAGPIO macro.

Reset mode

Polling input mode

Rising edge interrupt input mode

Falling edge interrupt input mode

Output mode

AUX output mode

Bidirectional mode.

Each pin can be used in input or output mode. Special hardware ports, which are capable of operating in three-state or open-drain mode are required to use this feature.

AMBA 2.0 APB interface

AMBA independent interrupt assertion line

Pin wise controllable polling mode

Pin wise controllable interrupt triggering on falling and rising input signal edges

Pin wise controllable multiplexing of auxiliary inputs

Pin wise controllable bidirectional I/O mode.

Functional description

The core has an AMBA APB bus communication interface and includes programmable registers that can be modified depending on the desired functionality.

Block Diagram

block diagram

Device Utilization & Performance

Technology	Device	Utilization (Average out of some different applications)	Performance
Stratix III (Altera)	EP3SL150F780C2	Logic Elements: 88 (8 bit width) Block Memory: 0	100 MHz AHB bus clock
ArriaGX (Altera)	EP1AGX90EF1152C6	Logic Elements: 105 Block Memory: 0	100 MHz AHB bus clock

GPIO

Technology

Device

Utilization

Performance