Industrial Reference Platform Features and Specifications

The following tables list the features, specifications, and the software package for the Industrial Reference Platform.

Intel^® Atom^™ Z530 Processor	Altera^® Arria^®GX EP1AGX90F1152-6 FPGA
Intel^®1.6-GHz processor frequency	TriMatrix memory structure performance up to 380 MHz
32-KB instruction and 24-KB data (L1) caches	12 transceiver channels (600 Mbps to 3.125 Gbps)
512-MB, 8-way set-associative L2 cache	Multiple clock networks, RAM blocks, and digital signal processing (DSP) blocks
533-MHz Front-Side Bus (FSB)	90,220 logic elements for system design
2.2-W maximum TDP (power)	Up to 538 I/O pins
13-mm x 14-mm package, PBGA 441 Socket	35-mm x 35-mm 1,152-pin FBGA package

System Features
Intel SCH US15W chipset with I/O controller on Qseven board (4.5 W)	2 x 20 characters LCD display and 8 LEDs for information display and system debug
1-GB DDR system memory	Factor clock and reset control
3x Gigabit Ethernet ports (1 PCIe module on Qseven, 2 ports on the FPGA board)	Eight input/8 output opto-isolated I/Os, 16 GPIOs, 5 push buttons, and 4 DIP switches
2x SATA-2 controllers (PCIe) module	2x CAN interfaces
250-GB HDD pre-installed with Linux OSADL	2x RS-485 fieldbus interfaces
DVI-D interface or internal LVDS backlit kit	2x RS-232 serial interfaces
Eight USB 2.0 ports	4x A/D and 4x D/A converters
SD card socket	Configuration FLASH
PCI Express x1 interface to the FPGA	Altera USB-Blaster^™
291-mm x 74-mm x 100-mm (L x W x H)	110/230VAC PSU (12V VDC input)
Hpe^®_desk development/debug tools, including JTAG debugger

Software Package	Free IP Evaluation Package from GE-Research
Linux OSADL	PCI Express X1 to connects FPGA with processor
3S CoDeSys IEC61131 run-time software (evaluation copy)	Ethernet, CAN, UART, I2C
Reference design examples	GPIO, Timer, Counter, Watchdog
Pre-installed reference platform configuration