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IP Handling
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OSS-ROM

General description Features

This core stores the parameters of the design during the generation of the top VHDL netlist.
This information is used by the operating system to initialize the drivers for the design.
We open the data structure if a developer wants to adapt his own OS.

 - AMBA 2.0 AHB interface
- Stores the following data:
  • IP identification
  • System clock
  • Interrupts
  • Address range
  • Generics
  • Pinning preset
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    Functional Description

    The core has an AMBA AHB bus communication interface.

     

    Block Diagram

     

    block diagram

     

     

    Device Utilization & Performance

    Technology

    Device

    Utilization

    (Average out of some different applications)

    Performance

    Stratix III

    (Altera)    		 EP3SL150F780C2

    Logic Elements: 77

    Block Memory: depends on numbers of IP

    100 MHz

    AHB bus clock

    ArriaGX

    (Altera)    		 EP1AGX90EF1152C6

    Logic Elements: 73

    Block Memory: depends on numbers of IP

    100 MHz

    AHB bus clock


     

     

     

     
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